There are a number of commercially available products which provide sensing, controlled and communications in a network environment. These products range from elaborate systems having a large amount of intelligence to simple systems having little intelligence. By way of example, such a system may provide control between a light switch and a light; when the light switch is operated, a digital code pattern is transmitted by one cell over power lines or free space and is received by another cell at the light. When the code is received, it is interpreted and subsequently used to control the light.
Such a system--comprising a network of intelligent cells in which the cells communicate, control and sense information--is described in U.S. Pat. No. 4,947,484, which application is assigned to the assignee of the present invention. FIG. 10 of U.S. Pat. No. 4,947,484 illustrates a block diagram of an intelligent cell capable of communicating, controlling and sensing information. As can be seen, such cells typically comprise a plurality of processors coupling an internal memory to an input/output (I/O) block across address and data buses. The memory portion of the intelligent cell may include a ROM for storing instructions, a RAM for buffer storage, and an EEPROM for holding configurable information or other information that needs to be retained in a non-volatile way. The I/O block includes a communications port having many functions programmed for various communications tasks. Observe that the intelligent cell of FIG. 10 further includes a clocking means and associated timing control elements.
Practically all processors require some means of transferring information either from an internal memory to an external communications port, or vis-a-versa. For example, in the processing system described in the above-referenced U.S. patent, a plurality of intelligent cells are shown being distributed along a network. These cells exchange information over some communications backbone, such as a transceiver. Individual cells each contain a multi-processor composed of several microprocessors. In a distributed intelligence environment such as this, where there exists a need to control or sense things remotely, cells are serviced by a communication port that allows each of the intelligent computers to communicate with all of the other intelligent computers over a variety of media.
Within this type of distributed environment, there may be certain applications for which the processing power inside individual cells may be inadequate. For instance, if a cell were given the task of controlling a factory floor and the algorithm used for calculating the control information were very compute-intensive (e.g., there were extensive multiplication or division calculations required) then there may also be a need to communicate between the intelligent cell and a high-speed industrial computer, e.g., a main frame computer capable of floating point operations. In such a situation, data transfer and communications within the cell takes place over a general purpose I/O bus coupled to an external port of the cell.
It is important to understand that the level of performance achieved in transferring information to/from a particular cell may not be governed by how fast the individual microprocessors perform within the cell, but by how fast the address and data pipelines (i.e., buses) operate between the memory and a communications port or between memory and an I/O port.
One traditional mechanism for communicating with memory is known as programmed I/O. According to the programmed I/O scheme, information is transferred a single byte at a time. For every byte of information to be transferred, the processor must execute an implicit instruction which, in the case of a data transfer out, first involves fetching a byte from a certain location within the RAM, then transferring it through the central processing unit (CPU) and then out to the communications port.
In other words, all processing is done on a byte-by-byte basis. In a given transfer (either into or out of the processing system), only a single byte is transferred for each cycle. In order to transfer multiple bytes (e.g., 256 bytes) in a programmed I/O scheme, single byte data must be repetitively moved from a location in RAM to the CPU, then from the CPU to the communications port. Each move requires execution of a separate processor instruction. Understandably, the primary drawbacks of programmed I/O are its extreme slowness and the burden it places on the CPU for transferring each byte.
In response to the relative slowness of programmed I/O, a mechanism referred to in the industry as direct-memory-access (DMA) was developed. DMA remains a popular way of transferring data between a memory and an I/O or communications port in a computer system which demands fast data transferring capability.
According to DMA, specialized controller circuitry is incorporated into both the memory and communications ports to allow each unit to directly seize control of the internal buses to access memory directly. As a result, DMA is an especially fast method of transferring data, particularly in a shared-memory architecture employing shared I/O buses.
The main problem with the DMA approach is that it involves a great deal of complexity. That is, there is a large amount of circuitry overhead associated with DMA for each of the participants. When implemented on an integrated circuit, one must realize that the superior performance of DMA comes at the expense of die area.
The reason for this is because a separate set of DMA hardware needs to be built into the communications port and each of the I/O blocks coupled to the internal data bus. DMA hardware normally comprises a state machine to seize control of the bus at precisely the right moment, and also some arbitration logic to insure that during DMA operations the microprocessor does not create a bus ownership conflict. Thus, while DMA offers a substantial increase in speed, this performance increase comes at the cost of a large hardware overhead.
The speed difference between DMA approaches and programmed I/O creates a dilemma for many intelligent cells of the type described which currently need to operate their communications and I/O ports at rates of approximately 1 Mbit/sec. In a typical cell of the type described, programmed I/O is approximately four times too slow to support the required communication rate, whereas direct memory access logic is at least an order of magnitude faster than needed. Recall the DMA circuitry generally requires a substantial increase in DMA-dedicated silicon area. (Buses and many other various signal must be brought together to accommodate DMA which requires a significant increase in routing area). In effect, DMA provides more performance than is needed at considerable additional cost.
Thus, there exists an unrequited need for an alternative to both programmed I/O and DMA, which operates at an intermediate data transfer rate.